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Training Objectives:

The understanding of ASIC design and implementation you'll get from this course will shed light on the lower layers of hardware devices you find yourself attacking or defending.

By the end of the training you will know how to convert a simple digital design into the files needed for ASIC fabrication. You will have the opportunity to apply to have your chip made on the Skywater 130nm process.

You will gain familiarity with the capabilities and possibilities of the new open source PDK (process design kit) and open source ASIC tools. You will learn:

• How MOSFETS are used as digital switches and how to draw and simulate your own using VLSI tools.
• How digital systems are built from standard cells provided by the PDK.
• How to convert your digital design into the files needed for ASIC fabrication using the OpenLANE ASIC flow.
• How to make an application to the free Google sponsored or paid ASIC

What to Expect? | Key Learning Objectives:

• Hands-on projects, supported with text guides and over 6 hours of videos.
• Learning in a friendly, relaxed, supportive environment.
• Links to relevant security topics: reverse engineering, hardware trojans, EMFI etc.
• Linux CLI and GUI usage.
• Digital design with Verilog.
• Opportunity to get your own chip fabricated on the free Google shuttle, or the $10k ChipIgnite program.
• You will retain access to the materials after the training is finished.

Training Detailed Description:

Each day we will start out together as a group, meet for lunch and then at the end of the day.

During the rest of the time you will be free to work on your own or in a small group. This gives flexibility for you to work at your own pace and explore the subject material. Matt & Guillem will be available to answer questions at all times.

Part 1: MOSFETs and the Skywater130 standard cells

MOSFETs are the building blocks of the chips we will be learning how to make. While we don’t need an in depth knowledge of how they work, it’s useful to see how they are joined together into functional blocks known as standard cells - for example AND gates or Flip-Flops.

• Basic understanding of how MOSFETs work.
• How are they constructed on a silicon wafer.
• How to run a simulation with ngspice.

Project 1.1: Choose a standard cell and simulate it

• Get an overview of what the standard cells are.
• Choose your favourite cell, simulate it and show it does what it should.
• Measure how fast it can propagate signals from input to output.

Project 1.2: Draw a mosfet in magic

• Learn the basics of the Magic VLSI tool.
• Extract the circuit from a drawing.
• Simulate with ngspice.

Part 2: Building Digital Designs

As we are focussing on digital design for making our ASIC we need to be able to efficiently describe the kind of hardware we want. Verilog is one of a few languages used for this purpose. It’s well supported by the open source tools.

At the same time we will be learning how to run simulations so you can test your designs as you go.

This part of the course can be done completely with simulation, or you can use an FPGA development board to help you.

The following topics will be covered:

• Designing digital circuits, data flow and control.
• Combinatorial logic.
• Sequential logic.
• Finite state machines.
• Modularity.

The labs are split up into the following projects, although if you already have some design skills you are free to choose other projects.

Project 2.1: RGB Colour mixer

• Build a Digital rotary encoder.
• Build a PWM driver.
• Combine them both to make a 3 channel RGB LED driver.

Project 2.2: Frequency counter

• Make an edge detector for an incoming digital signal.
• Build a 2 digit seven segment driver.
• Count edges in a fixed number of clock cycles and format to decimal.
• Use a state machine to sequence the conversion from binary to decimal.

Part 3: Formal Verification

We will take a quick look at Formal Verification and see how to use it to prove a digital design is working as desired.

• Bounded model checking.
• Assumptions and assertions.
• How to use the Open Source Formal Verification tools.

Project 3.1: Prove your design is safe

• Write a cover statement to show the timer starting and ending.
• Write some assertions to prove the timer works as designed.

Project 3.2: Prove the project wrapper is safe

• Put the RGB mixer design inside the project wrapper.
• Write some assertions that prove the design is safe in a multi project environment.
• Run the formal tools to make the proof.

Part 4: OpenLANE

OpenLANE is an automated set of tools to turn a digital design into the files needed for creating an ASIC. It is automated but it needs to be configured correctly to get usable results. We will cover:

• The different stages of the flow.
• How to interpret results, logs and errors.
• Design Rule Check (DRC)
• Layout vs Schematic (LVS)
• Basic configuration setting.

Project 4.1: harden an example design

• Choose an example design from the OpenLANE.
• Read the config and check the documentation.
• Run the tools and inspect the results.

Project 4.2: harden your design

• Use OpenLane to create the GDS files for your own design
• Learn how to resolve some basic errors
• Learn how to use the design exploration tools to help find the best results
• Make adjustments to your config for either personal or group submission.

Part 5: Google/Skywater/Efabless shuttle

The way to make ASIC fabrication cheaper is to parcel out the wafer into chunks and sell each chunk individually, this is known as a shuttle service or an MPW. Google has sponsored a shuttle service that will be running once every few months during 2021. Efabless are providing the intermediary services between the Skywater factory and applicants.

All applicants need to make use of a wrapper design called Caravel that encloses your own design. This wrapper includes a RISCV CPU, some memory and some peripherals. This can help take some of the burden off your own design as you can make use of existing peripherals.

We will be combining all the designs together using a special multiplexer harness I have developed. This allows us to put many independent designs into one application.

You will learn:

• The component parts of Caravel.
• How big a space there is inside for your designs.
• How to simulate it, including your own design.
• How to fulfil the application process and make your own application should you wish.

Project 5.1: Simulate your design inside Caravel

• Run Caravel’s example project’s test.
• Add your design to Caravel: design files, SoC firmware, testbench.
• Simulate your design within Caravel.

Project 5.2: Making a personal submission to Efabless

• Get your design’s GDS files in place.
• Build the final GDS for Caravel.
• Run the checker script.

Project 5.3: Making a group submission

• Wrap your small design ready for aggregating into the group submission.
• How to prepare your repository.
• Submit your design.

Who Should Attend? | Target Audience:

• Security researchers and engineers wanting a better understanding of how the lowest level of integrated digital systems work.
• Anyone who wants to get an ASIC fabricated free of charge or at a very low cost.
• Chip designers who want to quickly get to grips with the possibilities of the new open source PDK and tooling.

What to Bring? | Software and Hardware Requirements:

• Laptop / PC. Needs about 30GB free for the VM. 16GB RAM recommended. Virtualbox installed.
• Headset/headphones
• Optionally you can bring FPGA dev boards if you want to experiment with your digital designs on real hardware:
• Recommended FPBA board and PMODs:
• IceBreaker from 1bitsquared
• Dual seven segment PMOD
• Rotary Encoder PMOD

What to Bring? | Prerequisite Knowledge and Skills:

• Linux CLI experience
• Git experience
• Programming experience helpful but not required
• HDL (Verilog) experience useful but not required

Resources Provided at the Training | Deliverables:

• All training material are online
• Virtual Machine image.
• 3 IceBreaker FPGA boards to borrow during the digital design part of the course.

ABOUT THE TRAINERS

Matthew Venn is a renowned technology communicator who has recently completed his own Zero to ASIC journey. He brings 20 years of engineering experience to create excellent and innovative learning experiences for people all over the world. His online Zero to ASIC course has been very highly rated by participants. He submitted to the 1st Google tapeout in 2020, and the 2nd in June 2021 included 14 designs from course participants.

Guillem Cabo is a Research Engineer at the Barcelona Supercomputing Center (BSC), where he performs FPGA and ASIC design. He holds a M.Sc in Computer science focused on computer architecture and high-performance computing. He has participated in several academic RISC-V tapeouts and Google/Efabless MPW1.